www.kersemi.com 1 power mosfet irfr020, IRFU020, sihfr020, sihfu020 features ? halogen-free according to iec 61249-2-21 definition ? dynamic dv/dt rating ? surface mount (irfr020, sihfr020) ? available in tape and reel ?fast switching ? ease of paralleling ? simple drive requirements ? compliant to rohs directive 2002/95/ec description third generation power mosfets from vishay provide the designer with the best combi nation of fast switching, ruggedized device design , low on-resistance and cost-effectiveness. the dpak is designed for su rface mounting using vapor phase, infrared, or wave soldering techniques. note a. see device orientation. notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. v dd = 25 v, starting t j = 25 c, l = 541 h, r g = 25 , i as = 14 a (see fig. 12). c. i sd 17 a, di/dt 110 a/s, v dd v ds , t j 150 c. d. 1.6 mm from case. e. when mounted on 1" square pcb (fr-4 or g-10 material). product summary v ds (v) 60 r ds(on) ( )v gs = 10 v 0.10 q g (max.) (nc) 25 q gs (nc) 5.8 q gd (nc) 11 configuration single n-channel mosfet g d s dpak (to-252) ipak (to-251) g d s s d g d ordering information package dpak (to-252) dpak (to-252) ipak (to-251) lead (pb)-free and ha logen-free sihfr020-ge3 sihfr020tr-ge3 sihfu020-ge3 lead (pb)-free irfr020pbf irfr020trpbf a IRFU020pbf sihfr020-e3 sihfr020t-e3 a sihfu020-e3 snpb irfr020 irfr020tr a IRFU020 sihfr020 sihfr020t a sihfu020 absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 60 v gate-source voltage v gs 20 continuous drain current v gs at 10 v t c = 25 c i d 14 a t c = 100 c 9.0 pulsed drain current a i dm 56 linear derating factor 0.33 w/c linear derating factor (pcb mount) e 0.020 single pulse avalanche energy b e as 91 mj maximum power dissipation t c = 25 c p d 42 w maximum power dissipation (pcb mount) e t a = 25 c 2.5 peak diode recovery dv/dt c dv/dt 5.5 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 260 d document number: 90335 www.vishay.com s10-1122-rev. b, 10-may-10 1 power mosfet irfr020, IRFU020, sihfr020, sihfu020 vishay siliconix features ? halogen-free according to iec 61249-2-21 definition ? dynamic dv/dt rating ? surface mount (irfr020, sihfr020) ? available in tape and reel ?fast switching ? ease of paralleling ? simple drive requirements ? compliant to rohs directive 2002/95/ec description third generation power mosfets from vishay provide the designer with the best combi nation of fast switching, ruggedized device design , low on-resistance and cost-effectiveness. the dpak is designed for su rface mounting using vapor phase, infrared, or wave soldering techniques. note a. see device orientation. notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. v dd = 25 v, starting t j = 25 c, l = 541 h, r g = 25 : , i as = 14 a (see fig. 12). c. i sd d 17 a, di/dt d 110 a/s, v dd d v ds , t j d 150 c. d. 1.6 mm from case. e. when mounted on 1" square pcb (fr-4 or g-10 material). product summary v ds (v) 60 r ds(on) ( : )v gs = 10 v 0.10 q g (max.) (nc) 25 q gs (nc) 5.8 q gd (nc) 11 configuration single n-channel mosfet g d s dpak (to-252) ipak (to-251) g d s s d g d ordering information package dpak (to-252) dpak (to-252) ipak (to-251) lead (pb)-free and ha logen-free sihfr020-ge3 sihfr020tr-ge3 sihfu020-ge3 lead (pb)-free irfr020pbf irfr020trpbf a IRFU020pbf sihfr020-e3 sihfr020t-e3 a sihfu020-e3 snpb irfr020 irfr020tr a IRFU020 sihfr020 sihfr020t a sihfu020 absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 60 v gate-source voltage v gs 20 continuous drain current v gs at 10 v t c = 25 c i d 14 a t c = 100 c 9.0 pulsed drain current a i dm 56 linear derating factor 0.33 w/c linear derating factor (pcb mount) e 0.020 single pulse avalanche energy b e as 91 mj maximum power dissipation t c = 25 c p d 42 w maximum power dissipation (pcb mount) e t a = 25 c 2.5 peak diode recovery dv/dt c dv/dt 5.5 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 260 d * pb containing terminations are not rohs compliant, exemptions may apply
www.kersemi.com 2 irfr020, IRFU020, sihfr020, sihfu020 note a. when mounted on 1" square pcb (fr-4 or g-10 material). notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. pulse width 300 s; duty cycle 2 %. thermal resistance ratings parameter symbol min. typ. max. unit maximum junction-to-ambient r thja - - 110 c/w maximum junction-to-ambient (pcb mount) a r thja --50 maximum junction-to-case (drain) r thjc --3.0 specifications t j = 25 c, unless otherwise noted parameter symbol test condi tions min. typ. max. unit static drain-source brea kdown voltage v ds v gs = 0 v, i d = 250 a 60 - - v v ds temperature coefficient v ds /t j reference to 25 c, i d = 1 ma - 0.073 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = 60 v, v gs = 0 v - - 25 a v ds = 48 v, v gs = 0 v, t j = 125 c - - 250 drain-source on-state resistance r ds(on) v gs = 10 v i d = 8.4 a b - - 0.10 forward transconductance g fs v ds = 25 v, i d = 8.4 a 6.2 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 640 - pf output capacitance c oss - 360 - reverse transfer capacitance c rss -79- total gate charge q g v gs = 10 v i d = 17 a, v ds = 48 v, see fig. 6 and 13 b --25 nc gate-source charge q gs --5.8 gate-drain charge q gd --11 turn-on delay time t d(on) v dd = 30 v, i d = 17 a, r g = 18 , r d = 1.7 , see fig. 10 b -13- ns rise time t r -58- turn-off delay time t d(off) -25- fall time t f -42- internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact c -4.5- nh internal source inductance l s -7.5- drain-source body diode characteristics continuous source-dr ain diode current i s mosfet symbol showing the integral reverse p - n junction diode --14 a pulsed diode forward current a i sm --56 body diode voltage v sd t j = 25 c, i s = 14 a, v gs = 0 v b --1.5v body diode reverse recovery time t rr t j = 25 c, i f = 17 a, di/dt = 100 a/s b - 88 180 ns body diode reverse recovery charge q rr - 0.29 0.64 c forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s and l d ) d s g s d g www.vishay.com document number: 90335 2 s10-1122-rev. b, 10-may-10 irfr020, IRFU020, sihfr020, sihfu020 vishay siliconix note a. when mounted on 1" square pcb (fr-4 or g-10 material). notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. pulse width d 300 s; duty cycle d 2 %. thermal resistance ratings parameter symbol min. typ. max. unit maximum junction-to-ambient r thja - - 110 c/w maximum junction-to-ambient (pcb mount) a r thja --50 maximum junction-to-case (drain) r thjc --3.0 specifications t j = 25 c, unless otherwise noted parameter symbol test condi tions min. typ. max. unit static drain-source brea kdown voltage v ds v gs = 0 v, i d = 250 a 60 - - v v ds temperature coefficient ' v ds /t j reference to 25 c, i d = 1 ma - 0.073 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = 60 v, v gs = 0 v - - 25 a v ds = 48 v, v gs = 0 v, t j = 125 c - - 250 drain-source on-state resistance r ds(on) v gs = 10 v i d = 8.4 a b - - 0.10 : forward transconductance g fs v ds = 25 v, i d = 8.4 a 6.2 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 640 - pf output capacitance c oss - 360 - reverse transfer capacitance c rss -79- total gate charge q g v gs = 10 v i d = 17 a, v ds = 48 v, see fig. 6 and 13 b --25 nc gate-source charge q gs --5.8 gate-drain charge q gd --11 turn-on delay time t d(on) v dd = 30 v, i d = 17 a, r g = 18 : , r d = 1.7 : , see fig. 10 b -13- ns rise time t r -58- turn-off delay time t d(off) -25- fall time t f -42- internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact c -4.5- nh internal source inductance l s -7.5- drain-source body diode characteristics continuous source-dr ain diode current i s mosfet symbol showing the integral reverse p - n junction diode --14 a pulsed diode forward current a i sm --56 body diode voltage v sd t j = 25 c, i s = 14 a, v gs = 0 v b --1.5v body diode reverse recovery time t rr t j = 25 c, i f = 17 a, di/dt = 100 a/s b - 88 180 ns body diode reverse recovery charge q rr - 0.29 0.64 c forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s and l d ) d s g s d g
www.kersemi.com 3 irfr020, IRFU020, sihfr020, sihfu020 typical characteristics 25 c, unless otherwise noted fig. 1 - typical output characteristics, t c = 25 c fig. 2 - typical output characteristics, t c = 150 c fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature document number: 90335 www.vishay.com s10-1122-rev. b, 10-may-10 3 irfr020, IRFU020, sihfr020, sihfu020 vishay siliconix typical characteristics 25 c, unless otherwise noted fig. 1 - typical output characteristics, t c = 25 c fig. 2 - typical output characteristics, t c = 150 c fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature
www.kersemi.com 4 irfr020, IRFU020, sihfr020, sihfu020 fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area www.vishay.com document number: 90335 4 s10-1122-rev. b, 10-may-10 irfr020, IRFU020, sihfr020, sihfu020 vishay siliconix fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area
www.kersemi.com 5 irfr020, IRFU020, sihfr020, sihfu020 fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f document number: 90335 www.vishay.com s10-1122-rev. b, 10-may-10 5 irfr020, IRFU020, sihfr020, sihfu020 vishay siliconix fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f
www.kersemi.com 6 irfr020, IRFU020, sihfr020, sihfu020 fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit r g i as 0.01 t p d.u.t. l v ds + - v dd 10 v var y t p to obtain required i as i as v ds v dd v ds t p q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + - www.vishay.com document number: 90335 6 s10-1122-rev. b, 10-may-10 irfr020, IRFU020, sihfr020, sihfu020 vishay siliconix fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit r g i as 0.01 t p d.u.t. l v ds + - v dd 10 v var y t p to obtain required i as i as v ds v dd v ds t p q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
www.kersemi.com 7 irfr020, IRFU020, sihfr020, sihfu020 fig. 14 - for n-channel p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage rever s e recovery current body diode forward current v gs = 10 v a i s d driver gate drive d.u.t. l s d waveform d.u.t. v d s waveform inductor current d = p.w. period + - + + + - - - peak dio d e recovery d v/ d t test circuit v dd ? dv/dt controlled by r g ? driver s ame type a s d.u.t. ? i s d controlled by duty factor d ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low s tray inductance ? g round plane ? low leakage inductance current tran s former r g note a. v gs = 5 v for logic level device s v dd document number: 90335 www.vishay.com s10-1122-rev. b, 10-may-10 7 irfr020, IRFU020, sihfr020, sihfu020 vishay siliconix fig. 14 - for n-channel vishay siliconix maintains worldw ide manufacturing capability. prod ucts may be manufactured at on e of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents su ch as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?90335 . p.. period d/dt iode recovery dv/dt ripple 5 ody diode forward drop reapplied voltage rever s e recovery current ody diode forward current v s 0 v a s river gate drive ..t. l s waveform ..t. v s waveform nductor current p.. period peak io d e recovery d v/ d t test ircuit v dv/dt controlled by r g river s ame type a s ..t. s controlled by duty factor ..t. device under te s t ..t. ircuit layout con s ideration s ow s tray inductance round plane ow leakage inductance current tran s former r g ote a. v s 5 v for logic level device s v
www.kersemi.com 1 package information notes 1. package body sizes exclude mold flash, protrusion or gate bu rrs. mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side. 2. package body sizes determined at the outermo st extremes of the plastic body exclusive of mold flas h, gate burrs and interlea d flash, but including any mismatch between the top and bottom of the plastic body. 3. the package top may be smaller than the package bottom. 4. dimension "b" does not include dambar prot rusion. allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimens ion at maximum material condition. the dambar cannot be located on the lower radius of the foot. e b 3 l3 l4 b 2 e b d h e1 d1 a c2 l1 l2 c a1 l millimeters inches dim. min. max. min. max. e 6.40 6.73 0.252 0.265 l 1.40 1.77 0.055 0.070 l1 2.743 ref 0.108 ref l2 0.508 bsc 0.020 bsc l3 0.89 1.27 0.035 0.050 l4 0.64 1.01 0.025 0.040 d 6.00 6.22 0.236 0.245 h 9.40 10.40 0.370 0.409 b 0.64 0.88 0.025 0.035 b2 0.77 1.14 0.030 0.045 b3 5.21 5.46 0.205 0.215 e 2.286 bsc 0.090 bsc a 2.20 2.38 0.087 0.094 a1 0.00 0.13 0.000 0.005 c 0.45 0.60 0.018 0.024 c2 0.45 0.58 0.018 0.023 d1 5.30 - 0.209 - e1 4.40 - 0.173 - 0' 10' 0' 10' ecn: s-81965-rev. a, 15-sep-08 dwg: 5973 document number: 91344 www.vishay.com revision: 15-sep-08 1 package information vishay siliconix to-252aa (high voltage) notes 1. package body sizes exclude mold flash, protrusion or gate bu rrs. mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side. 2. package body sizes determined at the outermo st extremes of the plastic body exclusive of mold flas h, gate burrs and interlea d flash, but including any mismatch between the top and bottom of the plastic body. 3. the package top may be smaller than the package bottom. 4. dimension "b" does not include dambar prot rusion. allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimens ion at maximum material condition. the dambar cannot be located on the lower radius of the foot. e b 3 l3 l4 b 2 e b d h e1 d1 a c2 l1 l2 c a1 l millimeters inches dim. min. max. min. max. e 6.40 6.73 0.252 0.265 l 1.40 1.77 0.055 0.070 l1 2.743 ref 0.108 ref l2 0.508 bsc 0.020 bsc l3 0.89 1.27 0.035 0.050 l4 0.64 1.01 0.025 0.040 d 6.00 6.22 0.236 0.245 h 9.40 10.40 0.370 0.409 b 0.64 0.88 0.025 0.035 b2 0.77 1.14 0.030 0.045 b3 5.21 5.46 0.205 0.215 e 2.286 bsc 0.090 bsc a 2.20 2.38 0.087 0.094 a1 0.00 0.13 0.000 0.005 c 0.45 0.60 0.018 0.024 c2 0.45 0.58 0.018 0.023 d1 5.30 - 0.209 - e1 4.40 - 0.173 - t 0' 10' 0' 10' ecn: s-81965-rev. a, 15-sep-08 dwg: 5973
www.kersemi.com 1 package information notes 1. dimensioning and toler ancing per asme y14.5m-1994. 2. dimension are shown in inches and millimeters. 3. dimension d and e do not include mold flash. mold flash s hall not exceed 0.13 mm (0.005") per side. these dimensions are mea sured at the outermost extremes of the plastic body. 4. thermal pad contour optional with dimensions b4, l2, e1 and d1. 5. lead dimension uncontrolled in l3. 6. dimension b1, b3 and c1 apply to base metal only. 7. outline conforms to jedec outline to-251aa. base metal plating b 1, b 3 ( b , b 2) c1 (c) section b - b and c - c d a c2 c lead tip 5 5 (dat u m a) thermal pad e1 4 d1 v ie w a - a a1 a a c seating plane c c b b 1 2 b 4 4 4 3 5 l1 l l3 3 x b 2 3 x b 3 b 4 e 2 x e 0.010 c b m a 0.25 0.010 b a 0.25 l2 a c m millimeters inches millimeters inches dim. min. max. min. max. dim. min. max. min. max. a 2.18 2.39 0.086 0.094 d1 5.21 - 0.205 - a1 0.89 1.14 0.035 0.045 e 6.35 6.73 0.250 0.265 b 0.64 0.89 0.025 0.035 e1 4.32 - 0.170 - b1 0.65 0.79 0.026 0.031 e 2.29 bsc 2.29 bsc b2 0.76 1.14 0.030 0.045 l 8.89 9.65 0.350 0.380 b3 0.76 1.04 0.030 0.041 l1 1.91 2.29 0.075 0.090 b4 4.95 5.46 0.195 0.215 l2 0.89 1.27 0.035 0.050 c 0.46 0.61 0.018 0.024 l3 1.14 1.52 0.045 0.060 c1 0.41 0.56 0.016 0.022 1 0' 15' 0' 15' c2 0.46 0.86 0.018 0.034 2 25' 35' 25' 35' d 5.97 6.22 0.235 0.245 ecn: s-82111-rev. a, 15-sep-08 dwg: 5968 document number: 91362 www.vishay.com revision: 15-sep-08 1 package information vishay siliconix to-251aa (high voltage) notes 1. dimensioning and toler ancing per asme y14.5m-1994. 2. dimension are shown in inches and millimeters. 3. dimension d and e do not include mold flash. mold flash s hall not exceed 0.13 mm (0.005") per side. these dimensions are mea sured at the outermost extremes of the plastic body. 4. thermal pad contour optional with dimensions b4, l2, e1 and d1. 5. lead dimension uncontrolled in l3. 6. dimension b1, b3 and c1 apply to base metal only. 7. outline conforms to jedec outline to-251aa. base metal plating b 1, b 3 ( b , b 2) c1 (c) section b - b and c - c d a c2 c lead tip 5 5 (dat u m a) thermal pad e1 4 d1 v ie w a - a a1 a a c seating plane c c b b 1 2 b 4 4 4 3 5 l1 l l3 3 x b 2 3 x b 3 b 4 e 2 x e 0.010 c b m a 0.25 0.010 b a 0.25 l2 a c m millimeters inches millimeters inches dim. min. max. min. max. dim. min. max. min. max. a 2.18 2.39 0.086 0.094 d1 5.21 - 0.205 - a1 0.89 1.14 0.035 0.045 e 6.35 6.73 0.250 0.265 b 0.64 0.89 0.025 0.035 e1 4.32 - 0.170 - b1 0.65 0.79 0.026 0.031 e 2.29 bsc 2.29 bsc b2 0.76 1.14 0.030 0.045 l 8.89 9.65 0.350 0.380 b3 0.76 1.04 0.030 0.041 l1 1.91 2.29 0.075 0.090 b4 4.95 5.46 0.195 0.215 l2 0.89 1.27 0.035 0.050 c 0.46 0.61 0.018 0.024 l3 1.14 1.52 0.045 0.060 c1 0.41 0.56 0.016 0.022 t 1 0' 15' 0' 15' c2 0.46 0.86 0.018 0.034 t 2 25' 35' 25' 35' d 5.97 6.22 0.235 0.245 ecn: s-82111-rev. a, 15-sep-08 dwg: 5968
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